1. Field of the Invention
The present invention relates to a DC/DC converter, and more particularly to a DC/DC converter with which a stable output voltage can be obtained even when a difference between a supplied input voltage and an output voltage to be kept is small.
2. Description of the Related Art
A DC/DC converter (switching regulator) is a device for generating a predetermined output voltage from a supplied input voltage, and is mounted on various electric apparatus. Especially, an enormous number of DC/DC converters has been manufactured and marketed in recent years with the popularization of electronic devices of portable types.
FIG. 1 shows the basic configuration of a typical DC/DC converter. This DC/DC converter keeps an output voltage V.sub.out at a desired value by alternately closing (turning on) switches S1 and S2 at suitable timing. An input voltage V.sub.in, the output voltage V.sub.out, and a duty (duty cycle) D of the switch S1 (a ratio of time period in which the switch S1 is held ON to a switching cycle) fundamentally have the following relationship when the DC/DC converter is in a stable state. EQU D=V.sub.out /V.sub.in
FIG. 2 is a circuit diagram exemplifying a conventional DC/DC converter that accompanies a peak current control. A feedback amplifier (error amplifier) 1 generates a control signal I.sub.cntl for controlling the electric current flowing into an inductor L based on a difference between a voltage obtained by dividing an output voltage V.sub.out with resistors R1 and R2 and a reference voltage V.sub.ref. The level of the control signal I.sub.cntl rises with the decrease of the output voltage V.sub.out, and falls with the increase of the output voltage V.sub.out.
An oscillator 2 generates a pulse signal of a predetermined cycle. A ramp signal generating circuit 3 generates a ramp signal which is synchronous with the pulse signal output from the oscillator 2. Here, the ramp signal is a signal including a time period during which a voltage approximately linearly increases as time elapses. The ramp signal is used to stabilize the operations of the DC/DC converter. Details of the technique that utilizes a ramp signal in order to stabilize the operations of a DC/DC converter are disclosed, for example, by "On the Characteristics of DC-to-DC Converters Operating in Current Programmed Mode" written by K. Harada, et al. (the Telecommunications Society Paper, April '86, Vol.J69-C No. 4)
A comparator 4 generates a signal for resetting a latch circuit 5 based on the current signal IL representing an electric current flowing through the inductor L, the control signal I.sub.cntl generated by the feedback amplifier 1, and the ramp signal generated by the ramp signal generating circuit 3. Specifically, the comparator 4 generates the reset signal if the total of the current signal IL and the ramp signal is larger than the control signal I.sub.cntl.
The latch circuit 5 is set on the rising edge (or falling edge) of the pulse signal output from the oscillator 2, and is reset by the reset signal output from the comparator 4. When the latch circuit 5 is in a set state, the switches S1 and S2 are respectively held ON and OFF. In this state, the electric current from a DC power source toward a load flows via the switch S1 and the inductor L. The inductor current increases as time elapses.
If the inductor current increases and the total of the current signal IL and the ramp signal becomes larger than the control signal I.sub.cntl, the latch circuit 5 is reset. When the latch circuit 5 is in a reset state, the switches S1 and S2 are respectively held OFF and ON. In this state, the inductor current flows via the switch S2, and decreases with time. Thereafter, when the rising edge of the pulse signal from the oscillator 2 is input to the latch circuit 5, the latch circuit 5 is again set and the above described process is repeated.
In the above described operations, the control signal I.sub.cntl is controlled by the output voltage V.sub.out, which is kept under the feedback control at the voltage corresponding to the reference voltage V.sub.ref.
In the above described configuration, the switches S1 and S2 are normally implemented by semiconductor elements. Especially, a semiconductor switching element such as a MOS transistor, etc. is used as the switch S1. An n-type element (for example, an nMOS transistor) is desirable in consideration of the conditions such as low cost and less ON-resistance as the semiconductor switching element. However, the n-type semiconductor switching element requires a voltage which is higher than a power supply voltage V.sub.in when being driven.
FIG. 3 is a circuit diagram for explaining the circuit where a voltage higher than an input voltage is applied to the n-type semiconductor switching element. Here, the explanation will be provided by citing the switches S1 and S2, which are shown in FIG. 2, and their peripheral circuits as an example, and by assuming that the switch S1 is an nMOS transistor.
When the switch S1 is in an ON state (the state where the MOS transistor is ON), its drain-source is substantially short circuit. To turn on the switch S1, a voltage higher than a predetermined threshold voltage must be applied to between a gate and the source. That is, a voltage higher than the input voltage V.sub.in must be generated to turn on the switch S1. In this circuit, a voltage higher than the input voltage V.sub.in is generated by a boost capacitor CB, which is charged when the voltage of a node A sufficiently drops. Namely, the boost capacitor CB is charged when the switch S1 is OFF (the MOS transistor is turned off) and at the same time, the switch S2 is ON.
The input voltage V.sub.in supplied to the DC/DC converter may sometimes vary, especially when its power source is a battery. The DC/DC converter must keep the output voltage V.sub.out constant even in such a case. Accordingly, when the input voltage V.sub.in goes down, the process for increasing the duty D is performed according to the above described equation (1). That is, the ratio of time period in which the switch S1 is ON is increased.
As described above, however, the boost capacitor CB shown in FIG. 3 is charged when the switch S1 is OFF. Accordingly, if the duty D exceeds an upper limit, the boost capacitor CB cannot be fully charged, which leads to the disability of holding the switch S1 ON. This problem arises because a finite amount of time is required for a switching time, and a pulse width shorter than the switching cannot be generated. Accordingly, among existing DC/DC converters, a converter which regulates the maximum value of the duty D in order to fully charge the boost capacitor CB is known.
If the maximum value of the duty D is regulated, the relationship between the input voltage V.sub.in and the output voltage V.sub.out becomes as follows. EQU V.sub.out .ltoreq.V.sub.in .multidot.D.sub.max
Namely, if the maximum value of the duty D is regulated, a predetermined output voltage V.sub.out is difficult to be held when the input voltage V.sub.in goes down.